Product Type: Market Research Report
Published by: In-Stat
Published: September 2002
Product Code: R97-1058Description Network processors have experienced a lot of problems over the last year. While it was already a young and fragile market struggling to survive in a down economy on September 10, 2001, that attacks that happened a day later absolutely devastated the market. Upwards of 80% of the design wins that were healthy 15 months ago are dead today. However, through all of the gloom, the underlying principles that first attracted companies to NPUs remain. And it is these concepts that will eventually redeem this market - but it will take years longer than previously thought.
We carefully examined over 20 target markets to develop the Industry's most comprehensive report available on the true potential of this complex market. This 80-page report includes the normal in-depth technical overview, market overview, vendor profiles, market share analysis by revenue and by shipments for 2001 and the 1st half of 2002, and detailed, 5-year forecasts that are broken out by major market segments. By 2006, the total NPU market - including Metro and Core Grade NPUs - is projected to reach $1.6 Billion up from about $50 Million in 2001. Table of Contents - Executive Summary
- Introduction
- Methodology
- Technical Overview
- Definitions
- SONET Technology Review
- What is "Network Processing"
- Where do NPUs Fit Within a Nominal System?
- Why Use NPUs Instead of Other Solutions?
- ASICs versus NPUs
- Profit is Paramount
- The Evolving Internet
How important is software to NPUs?
- Market Overview
- History of the NPU Market
- Last Year's Problems
- Evidence of a Turn Around
- Patience is a Virtue
- The Hope of Tomorrow
- Harmonics are the Key
- Network Processor Forecast
- Forecast Process and Assumptions
- Overall Forecasts
- NPU Revenue Forecast 2001 to 2006
- NPU Shipments Forecast 2001 to 2006
- NPU ASP Forecast 2001 to 2006
- Summary
- Overall Penetration Rates
Forecasts by Speed Grade
- Metro NPUs
- Core NPUs
Market Shares
- Network Processor Vendors
- Agere Systems
- Applied Micro Circuits Corporation (AMCC)
- Bay Microsystems
- Broadcom
- Cognigine
- Mindspeed/Conexant
- EZchip Technologies
- Intel
- International Business Machines (IBM)
- Internet Machines Corp. (IMC)
- Motorola
- Silicon Access Networks, Inc.
- Teradiant Networks
- TranSwitch
- Vitesse
- Xelerated Packet Devices (XPD)
- Summary
- Appendix A: Glossary
- List of Tables
- Table 1. Speeds of the SONET and SDH Hierarchy
- Table 2. Terms used in NTC Layout Diagram
- Table 3. The Profit Curves Related to an ASIC-based Solution
- Table 4. The Profit Curves Related to an NPU-based Solution
- Table 5. Network Processor Revenue Forecast 2001 - 2006, ($M)
- Table 6. Network Processor Shipment Forecast 2001 - 2006 (Units in Thousands)
- Table 7. Network Processor ASP Forecast 2001 - 2006
- Table 8. Summary of Network Processor Market 2001 - 2006
- Table 9. Projected Penetration Rates for Merchant Metro NPUs, 2001 - 2006
- Table 10. Projected Penetration Rates for Merchant Core NPUs, 2001 - 2006
- Table 11. Metro NPU Revenue Splits, 2001 - 2006
- Table 12. Metro NPU Shipments 2001 - 2006 (Units)
- Table 13. Metro NPU Revenues 2001 - 2006, ($M)
- Table 14. Metro NPU Revenue Splits, 2001 - 2006
- Table 15. Core NPU Shipments 2001 - 2006
- Table 16. Core NPU Revenues 2001 - 2006, ($M)
- Table 17. Devices include in Market Share Analysis from Each NPU Vendor
- Table 18. Bill of Materials for a 320 Gbps NGCB using AMCC Devices
- List of Figures
- Figure 1. Summary of Network Processor Forecast ($B and Millions of Units)
- Figure 2. In-Stat/MDR's Market Segmentation for Network Processors
- Figure 3. The Fundamental Components of an SPE
- Figure 4. The Addition of a New ADM to a Typical MAN
- Figure 5. Types of Processor Architectures and Stage Timing
- Figure 6. Generalized NTC Layout Diagram
- Figure 7. Nominal Volume Curve for a Single NPU Project within a Single Target Market
- Figure 8. Compound Volume Curve for Many NPU Projects with Realistic Project Failures
- Figure 9. Amalgamation of Queue Managers and Fabric Interfaces into Traffic Mangers
- Figure 10. An NPU/TM/SF-Based NGCB handling Multiple Protocols
- Figure 11. AT&T's Internet Backbone Map
- Figure 12. Why Harmonics of 10 Gbps will be the Speeds of Choice to Connect Line Cards
- Figure 13. Network Processor Revenue Forecast 2001 - 2006 ($B)
- Figure 14. Network Processor Shipment Forecast 2001 - 2006
- Figure 15. Network Processor ASP Forecast 2001 - 2006
- Figure 16. Metro NPU Revenue Forecast ($M) 2001 - 2006
- Figure 17. Core NPU Revenue Forecast ($M) 2001 - 2006
- Figure 18. Market Shares by Revenues for Metro NPUs (%) 2001 and 1st Half 2002
- Figure 19. Market Shares by Shipments for Metro NPUs (%) 2001 and 1st Half 2002
- Figure 20. NP10 and TM10 configuration for OC-192
- Figure 21. RCUs and RSFs scaled to OC-192
- Figure 22. A Simple, NP-1-Based Solution
- Figure 23. Interface Versatility Resulting from use of QX-1
- Figure 24. Internal Block Diagram of the IXP2400
- Figure 25. The Basic Layout of Internet Machine's "3 Silicon Musketeers"
- Figure 26. Internal Block Diagram of Motorola's C-3e
- Figure 27. General Layout of Silicon Access' iFlow Network Processing Chipset
- Figure 28. How to Make a High Density Cross Connect with TranSwitch Products
- Figure 29. A Possible Layout Including the IQ2200 and the GigaStream Switch Fabric
- Figure 30. Internal Block Diagram of X10 NPU
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