Digital Engines in Base Transceiver Stations

The evolution of wireless connectivity to support increased system capacities, improved voice quality, multimedia services, and high-speed data transfers, is driving the introduction of flexible system architectures and the processors that can enable them. As designs for base transceiver stations progress toward 3G and beyond, the flexibility that is and will be required by evolving standards and by demands on performance, will be achieved by software algorithms and models such as employed in smart antenna arrays, software defined radio, and programs that help overcome multipath effects.

Implemented mostly using communication processors and general purpose Digital Signal Processors (DSP), base transceiver stations also require high-performance microprocessors to function as controllers and host processors. Special operating systems are used to support the communications between various processors and tasks and to ensure that partial failures will not affect the overall functionality of a base station transceiver. Digital Engines publications (DSPs for the 3G Wireless Infrastructure) and (Communications Processors: Weighing Architecture Alternatives) cover the DSP and communications chips. "Digital Engines In Base Transceiver Stations" presents an overview of the evolution of cellular communications and completes the picture by adding a review of the microprocessors that are used as controllers and host processors.

• Executive Summary
  
  
  


• Marketing Manager
  ’s Summary
  
  


• Methodology
  
  


• Nomenclature
  
  


• Introduction
  
  


• Business and Technology
  —an Overview
  
  


• A View of the Business
  
  
  
  
  
  
  • Responding
    to Increased Competition
    
    
  
  
  • Competing for
    the Last Mile and the Last Meters
    
    
  
  
  • Investment
    and Cost of Ownership
    
    
  
  
  
  


• Systems and Processors
  
  
  
  
  
  
  • Processes in
    BTS
    
    
  
  
  • Hardware:The
    System Architecture
    
    
  
  
  • Which Processor
    Is Best For the Job?
    
    
    
    
    
    • Implementation
      Alternatives
      
      
    
    
    • The Cost
      of Granularity
      
      
    
    
    • Fitting
      Processors to Workloads:ASICs,FPGAs,DSPs,and ASSPs
      
      
    
    
    • The MPU:System
      Management and Network Interface
      
      
    
    
    
    
  
  
  
  


• Trends in Systems
  and Processors
  
  
  
  
  
  • Multi Input
    Multi Output (MIMO)System Research
    
    
    
    
    
    • Dependency
      On Vehicle Speed
      
      
    
    
    
    
  
  
  • Roadmap For
    DSP and Memory
    
    
  
  
  
  


• The Business Forecast
  
  
  
  
  
  
  • Processor Shipments
    by End-Use
    
    
    
    
    
    • DSP Shipments
      2000 –2005
      
      
    
    
    • MPU Shipments
      2000 –2005
      
      
    
    
    
    
  
  
  • Processor Shipments
    By Workload
    
    
    
    
    
    • Processor
      Shipments Into CDMA Systems
      
      
    
    
    • Processor
      Shipments Into TDMA Systems
      
      
    
    
    • Processor
      Shipments Into GSM Systems
      
      
    
    
    
    
  
  
  
  


• Concluding Thoughts
  


• Appendix A:The
  MPU
  
  
  
  
  
  
  
  • Motorola
    ’s PowerQUICC MPC860
    
    
  
  
  • Motorola
    ’s PowerQUICC MPC8260
    
    
  
  
  • IBM ’s
    PowerPC 440GP
    
    
  
  
  
  
  
  


• Appendix B:Multiple
  Access Methods
  
  
  
  
  
  
  
  • Frequency
    Division Multiple Access (FDMA)
    
    
  
  
  • Narrow Frequency
    Multiple Access (NFDMA)
    
    
  
  
  • Time Division
    Multiple Access (TDMA
    
    
  
  
  • Code Division
    Multiple Access (CDMA
    
    
  
  
  • Direct Sequence
    Spread Spectrum
    
    
  
  
  • Frequency-Hopping
    Spread Spectrum
    
    
  
  
  • Area Division
    Multiple Access
    
    
  
  
  • Polarization
    Division Multiple Access
  
  
  
  
  
  

List of Tables

• Table 1.Worldwide
  unit processor shipments into BTS 2000 –2005
  
  


• Table 2.Features
  of cellular communication generations
  
  


• Table 3.BER vs.signal-to-noise
  ratio for vehicles in motion
  
  


• Table 4.An averaged
  DSP roadmap vs.memory BW 2000 –2005
  
  


• Table 5.Worldwide
  unit processor shipments for BTS infrastructure 2000 –2005
  
  


• Table 6.Worldwide
  DSP unit shipments by end-use 2000 –2005
  
  


• Table 7.MPU worldwide
  unit shipments into BTS 2000 –2005
  
  


• Table 8.Worldwide
  processor unit shipments in CDMA by type and workload 2000 –2005
  
  
  


• Table 9.Worldwide
  processor unit shipments in TDMA by type and workload 2000 –2005
  
  
  


• Table 10.Worldwide
  processor unit shipments in GSM by type and workload 2000 –2005
  

List of Figures

• Figure 1.Cellular
  architecture and control hierarchy
  
  


• Figure 2.A simplified
  block diagram of processes in BTS (2.5G-3G)
  
  


• Figure 3.Interleaving
  block diagram
  
  


• Figure 4.Direct
  sequence spread spectrum CDMA block diagram
  
  


• Figure 5.BTS system
  architecture for 1G and 2G
  
  


• Figure 6.BTS system
  architecture for 3G
  
  


• Figure 7.Programmable
  DSP array board diagram
  
  


• Figure 8.Array
  detail:one DSP processor,fixed of floating point
  
  


• Figure 9.MIMO receiver
  block diagram
  
  


• Figure 10.BER vs.signal-to-noise
  ratio for vehicles in motion
  
  


• Figure 11.Single
  DSP roadmap 2000 –2005
  
  


• Figure 12.Worldwide
  unit processor shipments for BTS infrastructure 2000 –2005
  
  


• Figure 13.Worldwide
  DSP unit shipments by end-use 2000 –2005
  
  


• Figure 14.Worldwide
  MPU unit shipments into BTS 2000 –2005


• Figure 15.Worldwide
  processor unit shipments in CDMA by type and workload 2000 –2005
  
  
  


• Figure 16.Worldwide
  processor unit shipments in TDMA by type and workload 2000 –2005
  
  
  


• Figure 17.Worldwide
  processor unit shipments in GSM by type and workload 2000 –2005
  
  
  


• Figure 18.Motorola
  ’s PowerQUICC MPC860 block diagram
  
  


• Figure 19.Motorola
  MPC8260 Block Diagram
  
  


• Figure 20.IBM ’s
  PowerPC 440GP block diagram
  
  


• Fig